an1578/1002 1/8 an1578 application note developing st92f250 applications using the st92f150-emu2 emulator by microcontroller division applications introduction the st92f150-emu2 emulator is built around the st92f150 device and can be used to em- ulate any of the family of the st92f124/f150/f250 devices. the purpose of this document is to present how to perform st92f250 emulation using the st92f150-emu2. the first part of this document lists the differences between the st92f250cv2 and the st92f150jdv1. the second part evaluates the restrictions that apply when using the st92f150 emulator to debug a st92f250 application. 1
2/8 developing st92f250 applications using the st92f150-emu2 emulator 1 st92f250 versus st92f150 table 1. st92f250cv2 versus st92f150jdv1 1.1 sci-a lin master a local interconnect network (lin) message frame starts with a 13-bit synch break. software lin master solutions are based on a standard asynchronous serial communication interface that generates a 10-bit break (continuous dominant low level). some software workarounds exist, for instance changing the baud rate before sending a synch break, but they have some limitations and they increase the code size. the st92f250 sci-a has a hardware feature for generating a 13-bit synch break this is possible in lin master mode which is entered by setting the line bit (bit 6 of the scicr3 register, r255 page 26). feature st92f150jdv1 st92f250cv2 emulation yes no ram size 6 kbytes 8 kbytes flash memory size 128 kbytes 256 kbytes can interfaces 21 j1850 (jblpd) interface yes no i2c interfaces 12 sci-a lin master no yes io and as/ds/rw drive programmable: standard or high drive standard: except p46 p47 p64 p65 wkup6 mapping p51/rx1 p51 io reset behavior refer to the errata sheet refer to the datasheet a[18:17] available not available when the i2c_1 is in use (when i2ccr.pe bit is set). p30, p66 and p67 no yes avdd parasitic diode yes, refer to the errata sheet no 2
3/8 developing st92f250 applications using the st92f150-emu2 emulator 1.2 i/o and as/ds/rw drive the high drive option (emr1.bsz bit=1) available in the st92f150 does not exist in the st92f250. this means that whatever the value of the bsz bit (bit 1 of the emr1 register, r245 page 21), the i io load current remains the same. table 2. maximum load current i io i this could impact an application ported from st92f150 to st92f250 in terms of external memory access speed (if emr1.bsz bit=1 in the application): C if the application code doesn't modify the reset state of the bsz bit, the external memory interface of the st92f250 will have the same timing characteristics as the st92f150. C if the application code modifies the reset state of the bsz bit, the external memory interface of the st92f250 will have different timing characteristics from the st92f150, and the appli- cation may have to be adapted by adding some wait cycles (refer to the external memory interface chapter of the datasheet). 1.3 wkup6 mapping the st92f120/f124/f150/f250 microcontrollers have a stop low power mode which can be exited by a wake-up event on the intd1 external interrupt channel. the wake-up event can be a rising or a falling event on one of the 16 wake-up lines: wkup[15:0] (refer to the wake-up / interrupt lines management unit chapter of the datasheet). in the st92f150, the wkup6 line is connected on both the can0 rx line (or p5.1 in standard i/o mode) and the can1 rx line. this is a useful feature for applications that use the can in- terfaces since an event on the can buses will wake-up the microcontroller. as the st92f250 includes only one can, the wkup6 line is connected only to the can0-rx (or p5.1 in standard i/o mode) and the pin corresponding to the can1 rx line becomes the standard i/o p6.6. application impact: if an st92f150 application uses the wkup6 line on the can1 rx line, this feature is not available on the st92f250 and the signal must be connected to another wake-up line (or on p5.1 wkup6). emr1.bsz=0 emr1.bsz=1 st92f150 st92f250 p4[7:6],p6[5:4] 4ma 16ma 16ma p0[7:0],p2[3:2], as ,ds ,rw 4ma 16ma 4ma all other pins except oscout 4ma 4ma 4ma
4/8 developing st92f250 applications using the st92f150-emu2 emulator 1.4 new p30, p66 and p67 standard i/o as the st92f250 does not include the j1850(jbld) and the second can peripheral, it has three additional standard input/output ports: C the p3.0, replacing the vpwo pin and providing a complete 8-pin p3 port. C the p6.6 and the p6.7, replacing the can1 rx and tx lines and providing a complete 8-pin p6 port. 1.5 flash 1.5.1 flash memory mapping to extend the flash memory size up to 256kbytes, two 64kbyte sectors have been added in the st92f250. these sectors f4 and f5 are mapped in the second and third memory seg- ments. 1.5.2 flash & e3 tm status register 0 (fesr0) the meaning of the four first bits of the fesr0 register (located at the addresses 224002h and 221002h) is modified to indicate the status of all the flash sectors. bit 6:0 = fess[6:0]. flash and e3 tm sectors status these bits are set by hardware and give the status of the 7 flash and e3 tm sectors. for st92f150 128k and 64k flash devices: C fess3:0 = flash sectors (f3:0) for the st92f250 256k flash device: C fess3 gives the status of f5, f4 and f3 sectors: the combined status of all these three sec- tors is ored on this bit. C fess2:0 = flash sectors (f2:0) 1.5.3 non volatile write protection register (nvwpr) the meaning of bit 3 of the nvwpr register (located at the address 231ffdh) is modified to take the f4 and f5 sectors into account. bit 3 = wprs3: flash sectors 5-3 write protection. this bit, if programmed to 0, disables any write access to flash sectors f3, f4, and f5.
5/8 developing st92f250 applications using the st92f150-emu2 emulator 2 st92f250 emulation as stated in the previous chapter, an st92f250 application with the following characteristics can be emulated by a st92f150 emulator without any restrictions: C second i2c not used. C sci-a lin master feature not used. C p3.0, p6.6 and p6.7 not used. C i/o configuration changed in the first step of the application code. C application not impacted by the adc parasitic diode. in all other cases the differences must be taken into account during the application develop- ment using the st92f150 emulation to anticipate the application behaviour on the st92f250. flash management and the new features (second i2c, sci-a lin master mode and new i/os) must be validated in the st92f250 device in the application. the following st9 hds2v2 emulators and emulation probes support upgrades and/or recon- figuration with new probe hardware: C st92f150-emu2 C st92f120-emu2 C st90158-emu2 and st90158-emu2b C st92141-emu2 C ST92163-EMU2 to upgrade a st92f120 emulator to a st92f150 emulator, refer to application note an977 guidelines for upgrading from the st92f120 (0.50m) to the st92f124 and st92f150 (0.35 m).
6/8 developing st92f250 applications using the st92f150-emu2 emulator 2.1 flash and ram memory areas the st9 emulator emulates the internal memory with a ram memory embedded in the emu- lator mainboard. all the st92f250 flash and ram memory areas can be emulated with a st92f150 emulator, with the limitations due to the ram and flash differences (program and erase process). to specify the device memory organization, use the emulator-> memory mapping menu, and st92f250 256kbyte flash device. figure 1. emulator memory mapping
7/8 developing st92f250 applications using the st92f150-emu2 emulator 2.2 sci-a lin master with the st92f150 emulator, the prescaler must be increased before sending the synch break and decreased before sending the synch field. for instance: C fcpu=24mhz, normal prescaler=75, baudrate=20kbps. bitlength=50us, synch- break=500us. C fcpu=24mhz, synch break prescaler=95, baudrate=15.8kbps. bitlengh=63.33us, break- length=506us. the second configuration can be used for the synch break generation and the first one for the other part of the lin frame (synch field, data and crc). this prescaler modification is only used for the application development using the emulator. the final st92f250 application uses just one prescaler and sets the line bit in the sci-a in- itialization code. 2.3 second i2c the i2c-1 cannot be emulated but the code validation can be done as a separate application using the i2c-0. when the i2c-1 is being used, external addresses a[18:17] are no longer available. this is not the case with the st92f150 emulator as the second i2c is not available. take care not to use these addresses. 2.4 external memory access the external memory access should be emulated with emr1.bsz bit=0. this will configure the p4[7:6]-p6[5:4] signals in standard mode. if high drive mode is needed for the i2c communication (with emr1.bsz bit=1), it should be emulated separately from the external memory access (with emr1.bsz bit=0). 2.5 p3.0, p6.6 and p6.7 these general purpose i/os cannot be emulated. 2.6 toolchain include files all the st92f250 features are described in the stvd9 v6 toolchain include files. use the following statement: #include #include #include #include
8/8 developing st92f250 applications using the st92f150-emu2 emulator the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connection with their products. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.stmcu.com
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